1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to audio data transmission and reception, and more particularly, to digital audio data transmission and reception using an I2S transmission scheme between ICs.
2. Description of the Related Art
In general, audio data transmission schemes include Inter-IC Sound (I2S), Sony/Philips Digital Interface (S/PDIF), and Audio Engineering Society/European Broadcasting Union (AES/EBU). The I2S is the most widely used to transmit 2-channel Pulse Code Modulation (PCM) audio data between an Analog Digital Converter (ADC), a Digital Analog Converter (DAC), and Integrated Circuits (ICs) of a Digital Signal Processor (DSP).
FIGS. 1A and 1B show audio data transmission and reception methods of the related art.
The audio data transmission and reception methods of FIGS. 1A and 1B relate to the I2S transmission scheme. The I2S transmission scheme transfers audio data through a channel select clock (hereafter, referred to as an LRCLK) line, a bit clock (hereafter, referred to as a BCLK) line, an audio sample data (hereafter, referred to as an SDATA) line, and a master clock (or a system clock) line.
In FIG. 1A, when the LRCLK is low, audio sample data of the left channel is transmitted along the SDATA line in serial. When the LRCLK is high, audio sample data of the right channel is transmitted along the SDATA line in serial. A reception side latches and reads the SDATA at the rising edge of the BCLK.
The audio sample data up to 32 bits (n=32) can be transmitted at one time when the LRCLK is low or high. 16-bit, 20-bit, 22-bit, or 24-bit audio sample data is typically transmitted. Considering audio quality, 16 bits are most frequently used. When transmitting up to 32-bit audio data, the transmission side does not send data over eight 6-bit null intervals excluding the actual audio sample data. Thus, the reception side does not process the null interval at all.
For instance, when the audio sampling frequency (Fs) is 48 kHz, the BCLK is 3.072 MHz because the BCLK is at most 64 times the LRCLK. In FIG. 1B, one period tBCLK of the BCLK is about 326 ns (1/3.072 MHz). A minimum hold time tDH required to normally latch the SDATA at the rising edge of the BCLK is typically about 10 ns. Since the minimum hold time tDH is much greater than 10 ns in FIG. 1B, the reception side can normally latch the SDATA.
As discussed above, as the SDATA is synchronized with the low level and the high level of the LRCLK, the I2S transmission scheme serially transmits the audio sample data of the left and right channels in sequence. Hence, the I2S transmission scheme is used mainly to transmit the 2-channel PCM audio data. To adopt the I2S transmission scheme to transmit 5.1 channel audio data, three I2S input/output (I/O) interfaces are required.
When the I2S transmission scheme is used to transmit audio data of a multi-channel such as 5.1 channel, the IC pin count increases and the increased circuit design raises the cost.